Too much delay fault coverage is a bad thing
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Searching for Common Ground Between Low Cost and High Performance ATE Systems
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Wafer-level modular testing of core-based SoCs
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Test scheduling for wafer-level test-during-burn-in of core-based SoCs
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System-on-Chip Test Architectures: Nanometer Design for Testability
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Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and test strategies for microarchitectural post-fabrication tuning
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Wafer-level defect screening for "big-D/small-A" mixed-signal SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Editor's note: For years, it has been common to run a test at wafer and then exactly thesame test again at package. This article shows how one company took adetailed look at the wafer/package test mix and adjusted it to reduce costwhile retaining quality.驴Rob Aitken, Artisan Components