IEEE Spectrum
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Accuracy Requirements in At-Speed Functional Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Too Much Delay Fault Coverage Is a Bad Thing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan vs. Functional Testing - A Comparative Effectiveness Study on Motorola's MMC2107TM
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
IEEE Design & Test
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Functional test-sequence grading at register-transfer level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes an experimental study tounderstand issues and requirements forstructural-based testing using low cost testers,compared to functional-based testing using expensivetesters. Several studies have been directed at theeffectiveness of various test methods, but noneexplicitly addressed issues involved in attempting toreplace functional vectors with scan vectors and nonecarried the experiment further by placing defectivechips into systems and running system tests. This paperdescribes the results of such an experiment and offersinsight into necessary requirements for reduction orelimination of functional tests.