Fault Models and Test Generation for OpAmp Circuits—The FFM
Journal of Electronic Testing: Theory and Applications
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Evaluation and Data on Defect-Oriented BIST Architecture for High-Speed PLL
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
Journal of Electronic Testing: Theory and Applications
Mixed Signal DFT: A Concise Overview
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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We propose a new defect-oriented testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST for a PLL is possible. Fault simulations using the 900MHz PLL from National Semiconductor Corp. show higher fault coverage than previous test methods.