Defect oriented testing for CMOS analog and digital circuits
Defect oriented testing for CMOS analog and digital circuits
Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops
IEEE Design & Test
Proceedings of the IEEE International Test Conference 2001
Power supply current monitoring techniques for testing PLLs
ATS '97 Proceedings of the 6th Asian Test Symposium
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Integration, the VLSI Journal
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Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase locked loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and Radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path (FP) gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter (LF) configurations.