Early Capture for Boundary Scan Timing Measurements
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test and Design Validity
A high speed and area efficient on-chip analog waveform extractor
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Digitizer Error Extraction in the Nonlinearity Test
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
A Statistical Sampler for a New On-Line Analog Test Method
Journal of Electronic Testing: Theory and Applications
RF-BIST: Loopback Spectral Signature Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning
Journal of Electronic Testing: Theory and Applications
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Estimation of RF PA Nonlinearities after Cross-correlating Current and Output Voltage
Journal of Electronic Testing: Theory and Applications
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An area efficient and robust integrated test corefor mixed-signal circuits is described. The core consists ofa completely digital implementation, except for a simplereconstruction filter and a comparator. It is capable ofboth generating arbitrary band-limited waveforms (forexcitation purposes) and coherently digitizing arbitraryperiodic analog waveforms (for DSP-based test andmeasurement). A prototype IC was fabricated in a 3.3 V0.35 mm CMOS process. It was demonstrated to performvarious curve tracing, timing, and spectrum analysis tasksat a sampling frequency of 20 MHz (which was onlylimited by our experimental setup) while taking up an areaequivalent to only about five thousand standard-cell 2-input NAND gates.