IEEE Spectrum
Introducing Core-Based System Design
IEEE Design & Test
Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Standard test interface language (STIL), extending the standard
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Role of Test Protocols in Testing Embedded-Core-Based System ICs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Challenges in testing core-based system ICs
IEEE Communications Magazine
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Test synthesis for mixed-signal SOC paths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing TAPed cores and wrapped cores with the same test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Using mission logic for embedded testing
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
ETM10 Incorporates Hardware Segment of IEEE P1500
IEEE Design & Test
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
CTL the Language for Describing Core-Based Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A BUILT-IN TIMING PARAMETRIC MEASUREMENT UNIT
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
Journal of Electronic Testing: Theory and Applications
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
A New FPGA for DSP Applications Integrating BIST Capabilities
Journal of Electronic Testing: Theory and Applications
A Built-In Parametric Timing Measurement Unit
IEEE Design & Test
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
An novel methodology for reducing SoC test data volume on FPGA-based testers
Proceedings of the conference on Design, automation and test in Europe
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Analysis of test data compression techniques emphasizing statistical coding schemes
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
An efficient link controller for test access to IP core-based embedded system chips
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
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Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test(SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test ofsuch core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustratesthrough a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. Note that thispaper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects theview of five active participants of the standardization committee on its current status.