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Communications of the ACM
IEEE Spectrum
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CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
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Proceedings of the conference on Design, automation and test in Europe
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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Proceedings of the IEEE International Test Conference 2001
The Role of Test Protocols in Testing Embedded-Core-Based System ICs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
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SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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ITC '99 Proceedings of the 1999 IEEE International Test Conference
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessor based self schedule and parallel BIST for system-on-a-chip
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.