Test vector decompression via cyclical scan chains and its application to testing core-based designs

Authors:
Abhijit Jas;Nur A. Touba
Affiliations:
-;-
Venue:
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Year:
1998

Citing 13
Cited 68

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

DAC '93 Proceedings of the 30th international Design Automation Conference
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Testing systems on a chip

IEEE Spectrum
Minimal Test Sets for Combinatorial Circuits

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Two-Dimensional Test Data Decompressor for Multiple Scan Designs

Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Width Compression for Built-In Self Testing

Proceedings of the IEEE International Test Conference
An Efficient Method for Compressing Test Data

Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500

Proceedings of the IEEE International Test Conference
Deterministic Pattern Generation for Weighted Random Pattern Testing

EDTC '96 Proceedings of the 1996 European conference on Design and Test
4.1 COMPACT: A Hybrid Method for Compressing Test Data

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Class of Test Generators for Built-In Testing

IEEE Transactions on Computers

Memory fault diagnosis by syndrome compression

Proceedings of the conference on Design, automation and test in Europe
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Proceedings of the conference on Design, automation and test in Europe
Test volume and application time reduction through scan chain concealment

Proceedings of the 38th annual Design Automation Conference
Combining low-power scan testing and test data compression for system-on-a-chip

Proceedings of the 38th annual Design Automation Conference
Selective-run built-in self-test using an embedded processor

Proceedings of the 12th ACM Great Lakes symposium on VLSI
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

Proceedings of the 39th annual Design Automation Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design

Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

Journal of Electronic Testing: Theory and Applications
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Journal of Electronic Testing: Theory and Applications
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

Journal of Electronic Testing: Theory and Applications
Test Resource Partitioning for SOCs

IEEE Design & Test
A novel scan architecture for power-efficient, rapid test

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Scan Vector Compression/Decompression Using Statistical Coding

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation

ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture

ITC '01 Proceedings of the 2001 IEEE International Test Conference
OPMISR: The Foundation for Compressed ATPG Vectors

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Tester Retargetable Patterns

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Test Sequencing Hardware for Structural Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs

IEEE Transactions on Computers
Test data compression and test time reduction using an embedded microprocessor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
CircularScan: A Scan Architecture for Test Cost Reduction

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

Journal of Electronic Testing: Theory and Applications
Changing the Scan Enable during Shift

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Evaluation of heuristic techniques for test vector ordering

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Combining dictionary coding and LFSR reseeding for test data compression

Proceedings of the 41st annual Design Automation Conference
Matrix-based software test data decompression for systems-on-a-chip

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Fast and energy-frugal deterministic test through efficient compression and compaction techniques

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Adjustable Width Linear Combinational Scan Vector Decompression

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Technique for High Ratio LZW Compression

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolutionary Optimization in Code-Based Test Compression

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Evaluation of Error-Resilience for Reliable Compression of Test Data

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reseeding-Based Test Set Embedding with Reduced Test Sequences

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression

Journal of Electronic Testing: Theory and Applications
Two dimensional reordering of functional test data for compression by ATE

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Enhancing error resilience for reliable compression of VLSI test data

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Application of Arithmetic Coding to Compression of VLSI Test Data

IEEE Transactions on Computers
A Huffman-based coding with efficient test application

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient test-data compression for IP cores using multilevel Huffman coding

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Survey of Test Vector Compression Techniques

IEEE Design & Test
Scan-BIST based on cluster analysis and the encoding of repeating sequences

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs

IEEE Transactions on Computers
Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal
A novel test-data compression technique using application-aware bitmask and dictionary selection methods

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low cost scan test by test correlation utilization

Journal of Computer Science and Technology
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

Journal of Electronic Testing: Theory and Applications
A Variable-Length Coding Adjustable for Compressed Test Application

IEICE - Transactions on Information and Systems
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression

IEICE - Transactions on Information and Systems
Reducing test application time, test data volume and test power through Virtual Chain Partition

Integration, the VLSI Journal
Scan-chain partition for high test-data compressibility and low shift power under routing constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple scan trees synthesis for test time/data and routing length reduction under output constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Run-length-based test data compression techniques: how far from entropy and power bounds?—a survey

VLSI Design
Test data compression using efficient bitmask and dictionary selection methods

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MICRO: a new hybrid test data compression/ decompression scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding

Integration, the VLSI Journal
Test data compression based on geometric shapes

Computers and Electrical Engineering
Test data compression using interval broadcast scan for embedded cores

Microelectronics Journal
A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal
Deterministic test vector compression / decompression using an embedded processor

EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

Journal of Signal Processing Systems
A modified scheme for simultaneous reduction of test data volume and testing power

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Overcoming post-silicon validation challenges through quick error detection (QED)

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.01

Visualization

Abstract

A novel test vector compression/decompressiontechnique is proposed for reducing the amount of testdata that must be stored on a tester and transferred toeach core when testing a core-based design. A smallamount of on-chip circuitry is used to reduce both the teststorage and test time required for testing a core-baseddesign. The fully specified test vectors provided by thecore vendor are stored in compressed form in the testermemory and transferred to the chip where they aredecompressed and applied to the core (the compression islossless). Instead of having to transfer each entire testvector from the tester to the core, a smaller amount ofcompressed data is transferred instead. This reduces theamount of test data that must be stored on the tester andhence reduces the total amount of test time required fortransferring the data with a given test data bandwidth.