Two-Dimensional Test Data Decompressor for Multiple Scan Designs

Test Data Decompression for Multiple Scan Designs with Boundary Scan

IEEE Transactions on Computers

Deterministic BIST with Multiple Scan Chains

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop

Deterministic BIST with multiple scan chains

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Test vector decompression via cyclical scan chains and its application to testing core-based designs

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A highly regular multi-phase reseeding technique for scan-based BIST

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Fast seed computation for reseeding shift register in test pattern compression

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Test Vector Encodin Usin Partial LFSR Reseedin

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Test-decompression mechanism using a variable-length multiple-polynomial LFSR

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Achieving high encoding efficiency with partial dynamic LFSR reseeding

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal

Improving linear test data compression

IEEE Transactions on Very Large Scale Integration (VLSI) Systems