Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On Linear Dependencies in Subspaces of LFSR-Generated Sequences
IEEE Transactions on Computers
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Two-Dimensional Test Data Decompressor for Multiple Scan Designs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Decompression of test data using variable-length seed LFSRs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Fast seed computation for reseeding shift register in test pattern compression
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Vector Encodin Usin Partial LFSR Reseedin
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
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The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs between test data volume and test application time while achieving a complete fault coverage for any fault model for which test cubes are obtainable. It also reduces bandwidth requirements, as all test cube transfers involve compressed data. The test patterns are generated by the reseeding of a two-dimensional hardware structure which is comprised of a linear feedback shift register (LFSR), a network of exclusive-or (XOR) gates used to scramble the bits of test vectors, and extra feedbacks which allow including internal scan flip-flops into the decompressor structure to minimize the area overhead. The test data decompressor operates in two modes: pseudorandom and deterministic. In the first mode, the pseudorandom pattern generator (PRPG) is used purely as a generator of test vectors. In the latter case, variable-length seeds are serially scanned through the boundary-scan interface into the PRPG and parts of internal scan chains and, subsequently, a decompression is performed in parallel by means of the PRPG and selected scan flip-flops interconnected to form the decompression device. Extensive experiments with the largest ISCAS' 89 benchmarks show that the proposed technique greatly reduces the amount of test data in a cost effective manner.