IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines
IEEE Transactions on Computers
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
On-chip test generation for combinational circuits by LFSR modification
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Test Cycle Count Reduction in a Parallel Scan BIST Environment
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 14th international symposium on Systems synthesis
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
A programmable multiple-sequence generator for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
A Gauss-elimination based PRPG for combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Deterministic Test Pattern Reproduction by a Counter
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Vector Encodin Usin Partial LFSR Reseedin
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Multiple Weight Set Calculation Algorithm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Testing strategies for networks on chip
Networks on chip
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient scan-based BIST scheme for low power testing of VLSI chips
Proceedings of the 2006 international symposium on Low power electronics and design
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits
ITC'94 Proceedings of the 1994 international conference on Test
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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