BIST hardware generator for mixed test scheme

Authors:
C. Dufaza;H. Viallon;C. Chevalier
Affiliations:
Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, UMR CNRS/UM2, 161 Rue Ada, 34392 Montpellier Cedex 05, FRANCE;Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, UMR CNRS/UM2, 161 Rue Ada, 34392 Montpellier Cedex 05, FRANCE;Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, UMR CNRS/UM2, 161 Rue Ada, 34392 Montpellier Cedex 05, FRANCE
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

Deterministic testing is by far the most interesting Built-in Self-Test (BIST) technique due to the minimal number of test patterns it requires and to its predefined fault coverage. However, such a technique is not applicable since despite their efficiency the existing deterministic test pattern generators are enormous consumers of overhead silicon area. Therefore, we propose a mixed test scheme which consists in applying to the circuit under test, a pseudo-random test sequence followed by a deterministic one obtained from an ATPG tool. This scheme allows a maximal fault coverage detection to be achieved for complex and realistic faults, e.g. stuck-at, stuck-open or delay faults, moreover, the silicon area overhead of the mixed hardware generator is drastically reduced. A compromise is to be found between the silicon area overhead of this generator and a slightly longer mixed test sequence. As an example, the additional circuitry requirements of the mixed test pattern hardware generator for the C3540 circuit are reduced to 20% of the nominal chip size for a total set of 1000 mixed test patterns.