Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Shift Register Sequences
A Multiple Seed Linear Feedback Shift Register
IEEE Transactions on Computers
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Decompression of test data using variable-length seed LFSRs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
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In complex systems, embedded processors may be used torun software routines for test pattern generation and responseevaluation. For system components which are not completelyrandom pattern testable, the test programs have to generatedeterministic patterns after random testing. Usually the randomtest part of the program requires long run times whereas thepart for deterministic testing has high memory requirements.In this paper it is shown that an appropriate selection of therandom pattern test method can significantly reduce the memoryrequirements of the deterministic part. A new, highly efficientscheme for software-based random pattern testing is proposed,and it is shown how to extend the scheme for deterministic testpattern generation. The entire test scheme may also be used forimplementing a scan based BIST in hardware.