Digital signal processing in VLSI
Digital signal processing in VLSI
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
BIST Pattern Generators Using Addition and Subtraction Operations
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
LFSR-Based Deterministic TPG for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Scan Array Solution for Testing Power and Testing Time
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper a novel accumulator-based Built-In Self Test (BIST) method for complete two-pattern test generation is presented. Complete two-pattern testing has been proposed for stuck-open and delay testing. The proposed scheme is very attractive for a wide range of circuits based on data-path architectures with arithmetic units, or with accumulators containing binary adders. Our method generates all 2/sup n/(2/sup n/-1) distinct two-pattern pairs for a n-input circuit under test within 2/sup n/(2/sup n/-1) clock cycles. The proposed method can be easily modified to generate complete two-pattern tests for circuits having k, (kn) inputs, within 2/sup k/(2/sup k/-1) clock cycles. Thus, this method is well-suited for circuits consisting of several modules with different number of inputs.