ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Optimal Vector Selection for Low Power BIST
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
BIST and Delay Fault Detection
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Accumulator-based BIST approach for stuck-open and delay fault testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper details a novel power estimation algorithmbased on Rate of Bit Propagation (RBP).Considering thereduction of RBP an advanced Scan Array architecture isproposed in which a wrapper and two dimensions scanchain is adopted.Estimated results based on RBP andexperiment results of industrial circuits both show thattesting power was reduced to the level of the functionalpower.Furthermore Pseudo-BIST is integrated with thewrapper to reduce the test time.