Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan Array Solution for Testing Power and Testing Time
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
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In order to meet the power and reliability constraints, it is important to reduce average power and peak power during test. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG), which can be used during on-line testing of large circuits requiring low power dissipation.The LPATPG can be implemented by linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by finding the best initial conditions in the CA cells.Results on ISCAS benchmark circuits show that average power reduction of up to 79.7%, peak power reduction of up to 39.2% and energy reduction of up to 84.4% can be achieved (compared to linear cellular automata) while achieving high fault coverage.