Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Modern heuristic techniques for combinatorial problems
Fault Coverage and Test Length Estimation for Random Pattern Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Effective low power BIST for datapaths (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Optimal Vector Selection for Low Power BIST
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Power Characterization of LFSRs
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
Evaluating BIST Architectures for Low Power
ATS '98 Proceedings of the 7th Asian Test Symposium
A New BIST Architecture for Low Power Circuits
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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Previous research has outlined that power dissipatedduring test application is substantially higher than duringfunctional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time howpower is minimized in BIST RTL data paths by using powerconscious test synthesis and test scheduling. According tothe necessity for achieving the required test efficiency powerdissipation is classified into necessary and useless powerdissipation. According to the occurrence during the testingprocess power dissipation is classified into test applicationand shifting power dissipation. The effect of test synthesisand scheduling on power dissipation is analyzed andpower minimization is achieved in two steps. Firstly, duringthe testable design space exploration only power conscioustest synthesis moves are accepted leading to minimizationof useless power dissipation. Secondly, module selectionduring power conscious test scheduling satisfies power constraints while reducing test application time. Experimentalresults using generic power models show savings up to 28%in test application power dissipation and up to 29% in shiftingpower dissipation.