Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Graph partitioning for concurrent test scheduling in VLSI circuit
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Hardware-optimal test register insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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