Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems
Journal of Electronic Testing: Theory and Applications
Efficient BIST hardware insertion with low test application time for synthesized data paths
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Journal of Biomedical Informatics
Configuring flip-flops to BIST registers
ITC'94 Proceedings of the 1994 international conference on Test
Towards an approach and framework for test-execution plan derivation
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
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