A knowledge based system for selecting a test methodology for a PLA
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Graph Theory With Applications
Graph Theory With Applications
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
Design for Testability A Survey
IEEE Transactions on Computers
IEEE Design & Test
Graph partitioning for concurrent test scheduling in VLSI circuit
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Test Scheduling in High Performance VLSI System Implementations
IEEE Transactions on Computers
Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic insertion of BIST hardware using VHDL
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High level test generation using data flow descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
EURO-DAC '91 Proceedings of the conference on European design automation
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
Journal of Electronic Testing: Theory and Applications
Control strategies for chip-based DFT/BIST hardware
ITC'94 Proceedings of the 1994 international conference on Test
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test scheduling for high performance VLSI system implementations
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence of actions that need to be carried out to execute the test. A theory of test plan execution overlap is presented, and is used as the basis for constructing test schedules with optimal execution times.