Testing Logic Networks and Designing for Testability

Authors:
T. W. Williams;K. P. Parker
Affiliations:
IBM;-
Venue:
Computer
Year:
1979

Citing 0
Cited 8

Test Schedules for VLSI Circuits Having Built-In Test Hardware

IEEE Transactions on Computers - The MIT Press scientific computation series
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design for Testability A Survey

IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits

IEEE Transactions on Computers
Design for Autonomous Test

IEEE Transactions on Computers
Design for Autonomous Test

IEEE Transactions on Computers
Automated diagnostic methodology for the IBM 3081 processor complex

IBM Journal of Research and Development
Test logic economic considerations in a commercial VLSI chip environment

ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production

Quantified Score

Hi-index	4.11

Visualization

Abstract

VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.