Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Generation of Fault Tests for Linear Logic Networks
IEEE Transactions on Computers
On Modifying Logic Networks to Improve Their Diagnosability
IEEE Transactions on Computers
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On Minimally Testable Logic Networks
IEEE Transactions on Computers
On Closedness and Test Complexity of Logic Circuits
IEEE Transactions on Computers
Minimum Parallel Binary Adders with NOR (NAND) Gates
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
Derivation of Minimal Test Sets for Monotonic Logic Circuits
IEEE Transactions on Computers
Universal Test Sets for Logic Networks
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design-for-testability techniques for CORDIC design
Microelectronics Journal
Parametric quantified SAT solving
Proceedings of the 2010 International Symposium on Symbolic and Algebraic Computation
A hierarchical environment for interactive test engineering
ITC'94 Proceedings of the 1994 international conference on Test
On the Complexity of Estimating the Size of a Test Set
IEEE Transactions on Computers
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testable design techniques for variable block size motion estimator used in H.264/AVC
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Efficient built-in self-test techniques for sequential fault testing of iterative logic arrays
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Formal Verification and Diagnosis of Combinational Circuit Designs with Propositional Logic
Fundamenta Informaticae
Fault detection in multi-core processors using chaotic maps
Proceedings of the 3rd Workshop on Fault-tolerance for HPC at extreme scale
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In this correspondence we analyze the computational complexity of fault detection problems for combinational circuits and propose an approach to design for testability. Although major fault detection problems have been known to be in general NP-complete, they were proven for rather complex circuits. In this correspondence we show that these are still NP-complete even for monotone circuits, and thus for unate circuits. We show that for k-level (k = 3) monotone/unate circuits these problems are still NP-complete, but that these are solvable in polynomial time for 2-level monotone/unate circuits. A class of circuits for which these fault detection problems are solvable in polynomial time is presented. Ripple-carry adders, decoder circuits, linear circuits, etc., belong to this class. A design approach is also presented in which an arbitrary given circuit is changed to such an easily testable circuit by inserting a few additional test-points.