A hierarchical environment for interactive test engineering

Authors:
T. Burch;J. Hartrnann;G. Hotz;M. Krallmann;U. Nikolaus;S. M. Reddy;U. Sparmann
Affiliations:
Computer Science Department, University of Saarland, Saarbrücken, Germany;Computer Science Department, University of Saarland, Saarbrücken, Germany;Computer Science Department, University of Saarland, Saarbrücken, Germany;Computer Science Department, University of Saarland, Saarbrücken, Germany;Computer Science Department, University of Saarland, Saarbrücken, Germany;Department of ECE, University of Iowa, Iowa City, Iowa;Computer Science Department, University of Saarland, Saarbrücken, Germany
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

Conventional tools for test generation and fault simulation appear to the test engineer as black boxes which neither communicate their results in a convenient way, nor allow for any interactive guidance by the test engineer. In contrast, the HIT system presented in this paper supports interactive test engineering, thus combining the power of gate level test generation algorithms with the high level knowledge of the test engineer. Since the HIT system has been integrated into a hierarchical design system (CADIC), the results of test tools can be visualized at the hierarchical circuit specifications given by the designer. Based on this visualization, the critical, untestable areas of the circuit can be easily located. Additionally, the test engineer is supplied with flexible test tools, which allow to actively guide the test development process. Thus, module specific test strategies can be applied or high level knowledge about the functionality of the overall circuit can be 'communicated' to speed-up test generation and redundancy identification. An application example shows that with simple strategies for interactive test engineering the results of test generation can be improved dramatically.