CHEETA: Composition of Hierarchical Sequential Tests Using ATKET

High-level synthesis for testability: a survey and perspective

DAC '96 Proceedings of the 33rd annual Design Automation Conference

BDD-based testability estimation of VHDL designs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Design for Testability Techniques at the Behavioraland Register-Transfer Levels

Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis

Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal

IEEE Transactions on Computers

Embedded hardware and software self-testing methodologies for processor cores

Proceedings of the 37th Annual Design Automation Conference

Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications

IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface

Journal of Electronic Testing: Theory and Applications

Implicit test generation for behavioral VHDL models

ITC '98 Proceedings of the 1998 IEEE International Test Conference

How to Avoid Random Walks in Hierarchical Test Path Identification

ETW '00 Proceedings of the IEEE European Test Workshop

DPDAT: DATA PATH DIRECT ACCESS TESTING

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A Novel Functional Test Generation Method for Processors using Commercial ATPG

ITC '97 Proceedings of the 1997 IEEE International Test Conference

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On the identification of modular test requirements for low cost hierarchical test path construction

Integration, the VLSI Journal

Satisfiability-based automatic test program generation and design for testability for microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Automatic constraint based test generation for behavioral HDL models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A hierarchical environment for interactive test engineering

ITC'94 Proceedings of the 1994 international conference on Test

Challenges in fault detection

FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing

Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems