Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On static compaction of test sequences for synchronous sequential circuits
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Generation of BDDs from hardware algorithm descriptions
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Approximation and decomposition of binary decision diagrams
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Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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Proceedings of the IEEE International Test Conference
How an "Evolving" Fault Model Improves the Behavioral Test Generation
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
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DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
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Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 12th ACM Great Lakes symposium on VLSI
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RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Behavioral test generation for the selection of BIST Logic
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RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
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ETW '00 Proceedings of the IEEE European Test Workshop
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AMLETO: A Multi-language Environment for Functional Test Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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International Journal of Parallel Programming
VFSim: concurrent fault simulation at register transfer level
Journal of Computer Science and Technology
Mixed hierarchical-functional fault models for targeting sequential cores
Journal of Systems Architecture: the EUROMICRO Journal
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Journal of Electronic Testing: Theory and Applications
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper proposes a behavioral-level test patterngeneration algorithm for behavioral VHDL descriptions.The proposed approach is based on the comparison between the implicit description of the fault-free behaviorand the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally showthat the test patterns generated at the behavioral levelprovide a very high stuck-at fault coverage when applied to different gate-level implementations of the givenVHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage,in particular when considering circuits with hard to detect faults.