Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Functional vector generation for HDL models using linear programming and 3-satisfiability
DAC '98 Proceedings of the 35th annual Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Introduction to High-Level Synthesis
IEEE Design & Test
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a non-scan gate-level Automatic Test Pattern Generation (ATPG) methodology which keeps the regularity in the arithmetic operations while reasoning about these operations for generating high-level test patterns from only faulty behavior of the design. Then by considering generated high-level test patterns as constraints and passing them to a SMT-solver we are able to automatically and efficiently generate gate-level test patterns. Experimental results show robustness and reliability of our method compared to other contemporary methods in terms of the fault coverage and CPU time.