Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Tearing based automatic abstraction for CTL model checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Formal verification in a commercial setting
DAC '97 Proceedings of the 34th annual Design Automation Conference
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validation with guided search of the state space
DAC '98 Proceedings of the 35th annual Design Automation Conference
Symbolic Model Checking
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Using Magnatic Disk Instead of Main Memory in the Murphi Verifier
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
An Iterative Approach to Language Containment
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
On Combining Formal and Informal Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior and testability preservation under the retiming transformation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliable verification using symbolic simulation with scalar values
Proceedings of the 37th Annual Design Automation Conference
Automatic lighthouse generation for directed state space search
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Rarity based guided state space search
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation coverage enhancement using test stimulus transformation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Advanced techniques for RTL debugging
Proceedings of the 40th annual Design Automation Conference
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
Using conjugate symmetries to enhance gate-level simulations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A framework for the functional verification of systemC models
International Journal of Parallel Programming
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
IEEE Transactions on Computers
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
IEEE Transactions on Computers
A novel collaborative scheme of simulation and model checking for system properties verification
Computers in Industry - Special issue: Collaborative environments for concurrent engineering
ICSE '07 Proceedings of the 29th international conference on Software Engineering
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Hybrid Verification of Protocol Bridges
IEEE Design & Test
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Formal Methods in System Design
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Model optimization techniques in a verification platform for classified properties
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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