Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Efficient breadth-first manipulation of binary decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BDD variable ordering for interacting finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Compilation of optimized OBDD-algorithms
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
On the Expressive Power of OKFDDs
Formal Methods in System Design
An Algorithm for Total Symmetric OBDD Detection
IEEE Transactions on Computers
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Parallel breadth-first BDD construction
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
Remembrance of things past: locality and memory in BDDs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
Safe BDD minimization using don't cares
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Approximation and decomposition of binary decision diagrams
DAC '98 Proceedings of the 35th annual Design Automation Conference
Don't care-based BDD minimization for embedded software
DAC '98 Proceedings of the 35th annual Design Automation Conference
Adaptive variable reordering for symbolic model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The design of a cache-friendly BDD library
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design of experiments in BDD variable ordering: lessons learned
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Symbolic reachability analysis of large finite state machines using don't cares
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Variable reordering for shared binary decision diagrams using output probabilities
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Speeding up symbolic model checking by accelerating dynamic variable reordering
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Proceedings of the 37th Annual Design Automation Conference
Efficient variable ordering using aBDD based sampling
Proceedings of the 37th Annual Design Automation Conference
Lazy group sifting for efficient symbolic state traversal of FSMs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient manipulation algorithms for linearly transformed BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Free MDD-based software optimization techniques for embedded systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
OBDD Minimization Based on Two-Level Representation of Boolean Functions
IEEE Transactions on Computers
Accurate and efficient predicate analysis with binary decision diagrams
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Binary decision diagram with minimum expected path length
Proceedings of the conference on Design, automation and test in Europe
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A hardware simulation engine based on decision diagrams (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The multiple variable order problem for binary decision diagrams: theory and practical application
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Symbolic Analysis of Bounded Petri Nets
IEEE Transactions on Computers
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
Formal Methods in System Design
Proceedings of the 38th annual Design Automation Conference
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 12th ACM Great Lakes symposium on VLSI
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
The nonapproximability of OBDD minimization
Information and Computation
Ordered binary decision diagrams
Logic Synthesis and Verification
A Comparison of Free BDDs and Transformed BDDs
Formal Methods in System Design
Data structures for Boolean functions
Computational Discrete Mathematics
Heuristic Learning Based on Genetic Programming
Genetic Programming and Evolvable Machines
Faster SAT and smaller BDDs via common function structure
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table
Formal Methods in System Design
Arithmetic Boolean Expression Manipulator Using BDDs
Formal Methods in System Design
The K*BMD: A Verification Data Structure
IEEE Design & Test
Design Verification of FPGA Implementations
IEEE Design & Test
The complexity of minimizing and learning OBDDs and FBDDs
Discrete Applied Mathematics
Integration, the VLSI Journal
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Lower bounds for linearly transformed OBDDs and FBDDs
Journal of Computer and System Sciences
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Formal Methods in System Design
Distributed Hybrid Genetic Programming for Learning Boolean Functions
PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature
BDD-Nodes Can Be More Expressive
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics
Proceedings of the International Conference, 7th Fuzzy Days on Computational Intelligence, Theory and Applications
Asymptotically Optimal Bounds for OBDDs and the Solution of Some Basic OBDD Problems
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Satisfiability Checking Using Boolean Expression Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Techniques for Smaller Intermediary BDDs
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Heuristic Learning Based on Genetic Programming
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Verifying Integrity of Decision Diagrams
SAFECOMP '98 Proceedings of the 17th International Conference on Computer Safety, Reliability and Security
k-Layer Straightline Crossing Minimization by Speeding Up Sifting
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
Error Detection with Directed Symbolic Model Checking
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Meta-BDDs: A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Extracting gate-level networks from simulation tables
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Journal of Symbolic Computation
Symbolic representation with ordered function templates
Proceedings of the 40th annual Design Automation Conference
Information and Computation - Special issue: LICS'97
Handbook of automated reasoning
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fast and Efficient Construction of BDDs by Reordering Based Synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
Efficient variable ordering and partial representation algorithm
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A study of composition schemes for mixed apply/compose based construction of ROBDDs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Verification of Digital Systems
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A genetic algorithm for decomposition type choice in OKFDDs
INBS '95 Proceedings of the First International Symposium on Intelligence in Neural and Biological Systems (INBS'95)
Algorithms and heuristics in VLSI design
Experimental algorithmics
From type inference to configuration
The essence of computation
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
Breaking cycles for minimizing crossings
Journal of Experimental Algorithmics (JEA)
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
BDDs: design, analysis, complexity, and applications
Discrete Applied Mathematics - Optimal discrete structure and algorithms (ODSA 2000)
Orthogonal hypergraph routing for improved visibility
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A method to decompose multiple-output logic functions
Proceedings of the 41st annual Design Automation Conference
Representation of Logical Circuits by Linear Decision Diagrams with Extension to Nanostructures
Automation and Remote Control
Automation and Remote Control
The Compositional Far Side of Image Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Ackermann encoding, bisimulations and OBDDs
Theory and Practice of Logic Programming
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Minimization of memory size for heterogeneous MDDs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combining ordered best-first search with branch and bound for exact BDD minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combination of Lower Bounds in Exact BDD Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 42nd annual Design Automation Conference
Quasi-Exact BDD Minimization Using Relaxed Best-First Search
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Application of Wu's method to symbolic model checking
Proceedings of the 2005 international symposium on Symbolic and algebraic computation
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
BDD-based verification of scalable designs
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
An anytime symmetry detection algorithm for ROBDDs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fast logic simulator using a look up table cascade emulator
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A BDD-based fast heuristic algorithm for disjoint decomposition
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Lower bounds for dynamic BDD reordering
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Logic and stochastic modeling with SMART
Performance Evaluation - Modelling techniques and tools for computer performance evaluation
Distributed dynamic BDD reordering
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 12th ACM SIGKDD international conference on Knowledge discovery and data mining
The octahedron abstract domain
Science of Computer Programming
IEEE Intelligent Systems
A Radial Adaptation of the Sugiyama Framework for Visualizing Hierarchical Information
IEEE Transactions on Visualization and Computer Graphics
IEEE Transactions on Computers
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
Binary decision diagrams: a mathematical model for the path-related objective functions
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Minimization of multiway decision graphs for RTL verification by stochastic optimization
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Formal Verification of a Flash Memory Device Driver --- An Experience Report
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Efficient compilation techniques for large scale feature models
GPCE '08 Proceedings of the 7th international conference on Generative programming and component engineering
Visualizing potential parallelism in sequential programs
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Automatic non-interference lemmas for parameterized model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
HS-ROBDD: an efficient variable order binary decision diagram
Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers
Group-Level Analysis and Visualization of Social Networks
Algorithmics of Large and Complex Networks
Weighted A∗ search -- unifying view and application
Artificial Intelligence
A genetic algorithm for the construction of small and highly testable OKFDD-circuits
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
Learning to order BDD variables in verification
Journal of Artificial Intelligence Research
Constraint and variable ordering heuristics for compiling configuration problems
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Symbolic state traversal for WCET analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
BDD-based synthesis of reversible logic for large functions
Proceedings of the 46th Annual Design Automation Conference
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Crossing minimization in extended level drawings of graphs
Discrete Applied Mathematics
Modeling Service Level Agreements with Binary Decision Diagrams
ICSOC-ServiceWave '09 Proceedings of the 7th International Joint Conference on Service-Oriented Computing
BDDs-design, analysis, complexity, and applications
Discrete Applied Mathematics
FSM Encoding for BDD Representations
International Journal of Applied Mathematics and Computer Science
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
A framework for quasi-exact optimization using relaxed best-first search
KI'06 Proceedings of the 29th annual German conference on Artificial intelligence
Symbolic archive representation for a fast nondominance test
EMO'07 Proceedings of the 4th international conference on Evolutionary multi-criterion optimization
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A microcanonical optimization algorithm for BDD minimization problem
IEA/AIE'07 Proceedings of the 20th international conference on Industrial, engineering, and other applications of applied intelligent systems
Multi-circular layout of micro/macro graphs
GD'07 Proceedings of the 15th international conference on Graph drawing
Journal of Visual Languages and Computing
Variable compression in ProbLog
LPAR'10 Proceedings of the 17th international conference on Logic for programming, artificial intelligence, and reasoning
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbolic model checking of probabilistic knowledge
Proceedings of the 13th Conference on Theoretical Aspects of Rationality and Knowledge
Implicit permutation enumeration networks and binary decision diagrams reordering
Proceedings of the 48th Design Automation Conference
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
Evolving binary decision diagrams with emergent variable orderings
PPSN'06 Proceedings of the 9th international conference on Parallel Problem Solving from Nature
Verifying very large industrial circuits using 100 processes and beyond
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Genetic algorithms for the variable ordering problem of binary decision diagrams
FOGA'05 Proceedings of the 8th international conference on Foundations of Genetic Algorithms
BDDs in a branch and cut framework
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
Crossing reduction in circular layouts
WG'04 Proceedings of the 30th international conference on Graph-Theoretic Concepts in Computer Science
Model-based variable and transition orderings for efficient symbolic model checking
FM'06 Proceedings of the 14th international conference on Formal Methods
A global k-level crossing reduction algorithm
WALCOM'10 Proceedings of the 4th international conference on Algorithms and Computation
New metrics for static variable ordering in decision diagrams
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Widening ROBDDs with prime implicants
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Dynamic segregative genetic algorithm for optimizing the variable ordering of ROBDDs
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Grid sifting: Leveling and crossing reduction
Journal of Experimental Algorithmics (JEA)
Solving compressed right hand side equation systems with linear absorption
SETA'12 Proceedings of the 7th international conference on Sequences and Their Applications
ICSOC'12 Proceedings of the 10th international conference on Service-Oriented Computing
BDD-Based Synthesis of Reversible Logic
International Journal of Applied Metaheuristic Computing
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