Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Error control systems for digital communication and storage
Error control systems for digital communication and storage
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Cryptography and network security (2nd ed.): principles and practice
Cryptography and network security (2nd ed.): principles and practice
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Fast Algorithms for Digital Signal Processing
Fast Algorithms for Digital Signal Processing
Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions
ISMVL '97 Proceedings of the 27th International Symposium on Multiple-Valued Logic
On the Construction of Multiple-Valued Decision Diagrams
ISMVL '02 Proceedings of the 32nd International Symposium on Multiple-Valued Logic
Proceedings of the conference on Design, automation and test in Europe
Selection of Efficient Re-Ordering Heuristics for MDD Construction
ISMVL '01 Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
IEEE Transactions on Computers
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
MODD for CF: a representation for fast evaluation of multiple-output functions
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
GASIM: a fast Galois field based simulator for functional model
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
A Theory of Galois Switching Functions
IEEE Transactions on Computers
| Hi-index | 14.98 |
This paper presents a technique for representing multiple output binary and word-level functions in GF(N) ($N=p^m$, p a prime number and m a nonzero positive integer) based on decision diagrams (DD). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks including integer multiplier circuits and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared BDDs. The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(N) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All these results reflect that the proposed technique can out perform existing techniques.