Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Compiling Verilog into timed finite state machines
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
The maximal VHDL subset with a cycle-level abstraction
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Fast hardware/software co-simulation for virtual prototyping and trade-off analysis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Enhanced visibility and performance in functional verification by reconstruction
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Digital system simulation: methodologies and examples
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid techniques for fast functional simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle-based simulation with decision diagrams
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Free MDD-based software optimization techniques for embedded systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A hardware simulation engine based on decision diagrams (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The multiple variable order problem for binary decision diagrams: theory and practical application
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Generalized cofactoring for logic function evaluation
Proceedings of the 40th annual Design Automation Conference
Some Recent Advances in Software and Hardware Logic Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Minimization of memory size for heterogeneous MDDs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
A fast logic simulator using a look up table cascade emulator
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
A Parallel Branching Program Machine for Emulation of Sequential Circuits
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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Abstract: An approach for fast discrete function evaluation based on multi-valued decision diagrams (MDD) is proposed. The MDD for a logic function is translated into a table on, which function evaluation is performed by a sequence of address lookups. The value of a function for a given input assignment is obtained with at most one lookup per input. The main application is to cycle-based logic simulation of digital circuits, where the principal difference from other logic simulators is that only values of the output and latch ports are computed. Theoretically, decision-diagram based function evaluation offers orders-of-magnitude potential speedup over traditional logic simulation methods. In practice, memory bandwidth becomes the dominant consideration on large designs. We describe techniques to optimize usage of the memory hierarchy.