Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ACM Computing Surveys (CSUR)
An optimal evaluation of Boolean expressions in an online query system
Communications of the ACM
Binary decision diagram with minimum expected path length
Proceedings of the conference on Design, automation and test in Europe
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
Automatic Construction of Decision Trees from Data: A Multi-Disciplinary Survey
Data Mining and Knowledge Discovery
Automated synthesis of efficient binary decoders for retargetable software toolkits
Proceedings of the 40th annual Design Automation Conference
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computers
A Parallel Branching Program Machine for Emulation of Sequential Circuits
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special significance when BDDs are used in simulation and design verification. A main result of this paper is that the APL for benchmark functions is typically much smaller than for random functions. That is, for the set of all functions, we show that the average APL is close to the maximum path length, whereas benchmark functions show a remarkably small APL. Surprisingly, however, typical functions do not achieve the absolute maximum APL. We show that the parity functions are unique in having that distinction. We show that the APL of a BDD can vary considerably with variable ordering. We derive the APL for various functions, including the AND, OR, threshold, Achilles' heel, and certain arithmetic functions. We show that the unate cascade functions uniquely achieve the absolute minimum APL.