A Parallel Branching Program Machine for Emulation of Sequential Circuits

Authors:
Hiroki Nakahara;Tsutomu Sasao;Munehiro Matsuura;Yoshifumi Kawamura
Affiliations:
Kyushu Institute of Technology, Japan;Kyushu Institute of Technology, Japan;Kyushu Institute of Technology, Japan;Renesas Technology Corp., Japan
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We emulated many benchmark circuits on PBM128, and compared its memory size and computation time with the Intel's Core2Duo microprocessor. PBM128 requires approximately quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo.