Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
LCC simulators speed development of synchronous hardware
Computer Design
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Modified branching programs and their computational power
Modified branching programs and their computational power
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Probabilistic construction and manipulation of free Boolean diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Exclusive simulation of activity in digital networks
Communications of the ACM
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Fast hardware/software co-simulation for virtual prototyping and trade-off analysis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hybrid verification using saturated simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hybrid techniques for fast functional simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle-based simulation with decision diagrams
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Free MDD-based software optimization techniques for embedded systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A hardware simulation engine based on decision diagrams (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
The multiple variable order problem for binary decision diagrams: theory and practical application
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Integration, the VLSI Journal
Generalized cofactoring for logic function evaluation
Proceedings of the 40th annual Design Automation Conference
Some Recent Advances in Software and Hardware Logic Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A method to decompose multiple-output logic functions
Proceedings of the 41st annual Design Automation Conference
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
A fast logic simulator using a look up table cascade emulator
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Parallel Branching Program Machine for Emulation of Sequential Circuits
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Separate compilation for synchronous modules
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
| Hi-index | 0.01 |
Abstract: This paper addresses the problem of speeding up functional (delay-independent) logic simulation for synchronous digital systems. The problem needs very little new motivation-cycle-based functional simulation is the largest consumer of computing cycles in system design. Most existing simulators for this task can he classified as being either event driven or levelized compiled-code, with the levelized compiled code simulators generally being considered faster for this task. An alternative technique, based on evaluation using branching programs, was suggested about a decade ago in the context of switch level functional simulation. However, this had very limited application since it could not handle the large circuits encountered in practice. This paper resurrects the basic idea present this technique and provides significant modifications that enable its application to contemporary industrial strength circuits. We present experimental results that demonstrate up to a 10X speedup over levelized compiled code simulation for a large suite of benchmark circuits as well as for industrial examples with over 40.000 gates.