The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Synthesis of software programs for embedded control application
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Esterel: a formal method applied to avionic software development
Science of Computer Programming
Tutorial: Compiling concurrent languages for sequential processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizations for a simulator construction system supporting reusable components
Proceedings of the 40th annual Design Automation Conference
Optimizations for Faster Execution of Esterel Programs
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
The semantics and execution of a synchronous block-diagram language
Science of Computer Programming
The liberty structural specification language: a high-level modeling language for component reuse
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Generating fast code from concurrent program dependence graphs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Modularity vs. reusability: code generation from synchronous block diagrams
Proceedings of the conference on Design, automation and test in Europe
Separate compilation for synchronous programs
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
A higher-order extension for imperative synchronous languages
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Separate compilation and execution of imperative synchronous modules
Proceedings of the Conference on Design, Automation and Test in Europe
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Synchronous models are useful for designing real-time embedded systems because they provide timing control and deterministic concurrency. However, the semantics of such models usually require an entire system to be compiled at once to analyze the dependencies among modules. The alternative is to write modules that can respond when the values of some of their inputs are unknown, a tedious and error-prone process. We present a compilation technique that allows a programmer to describe synchronous modules without having to consider undefined inputs. Our algorithm transforms such a description into code that does as much as it can with undefined inputs, allowing modules to be compiled separately and assembled later. We implemented our technique in a compiler for the Esterel language and present results that show the technique does not impose a substantial overhead.