Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Graph driven BDDs—a new data structure for Boolean functions
Theoretical Computer Science
Efficient OBDD-based boolean manipulation in CAD beyond current limits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A lower bound for integer multiplication with read-once branching programs
STOC '95 Proceedings of the twenty-seventh annual ACM symposium on Theory of computing
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Switching activity analysis for sequential circuits using Boolean approximation method
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
An efficient assertion checker for combinational properties
DAC '97 Proceedings of the 34th annual Design Automation Conference
Watermarking techniques for intellectual property protection
DAC '98 Proceedings of the 35th annual Design Automation Conference
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Forensic engineering techniques for VLSI CAD tools
Proceedings of the 37th Annual Design Automation Conference
A system-level co-verification environment for ATM hardware design
Proceedings of the conference on Design, automation and test in Europe
A formal approach to component based development of synchronous programs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Proceedings of the 12th ACM Great Lakes symposium on VLSI
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Proceedings of the 2002 international symposium on Physical design
The nonapproximability of OBDD minimization
Information and Computation
On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division
Formal Methods in System Design
Bounded model checking for the universal fragment of CTL
Fundamenta Informaticae
Observable Time Windows: Verifying High-Level Synthesis Results
IEEE Design & Test
Integration, the VLSI Journal
A Performance Study of BDD-Based Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Satisfiability Checking Using Boolean Expression Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Reducing Model Checking from Multi-valued {\rm CTL}^{\ast} to {\rm CTL}^{\ast}
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
Computational Forensic Techniques for Intellectual Property Protection
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Synchronized Product of Linear Bounded Machines
FCT '99 Proceedings of the 12th International Symposium on Fundamentals of Computation Theory
Extracting gate-level networks from simulation tables
ITC '98 Proceedings of the 1998 IEEE International Test Conference
MuTaTe: an efficient design for testability technique for multiplexor based circuits
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Fast and Efficient Construction of BDDs by Reordering Based Synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Symbolic counter-example generation for model checking
AEE'08 Proceedings of the 7th WSEAS International Conference on Application of Electrical Engineering
Error propagation analysis for file systems
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decision diagrams for the computation of semiring valuations
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Bounded Semantics of CTL and SAT-Based Verification
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model checking with SAT-based characterization of ACTL formulas
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
Expect the unexpected: error code mismatches between documentation and the real world
Proceedings of the 9th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defective error/pointer interactions in the Linux kernel
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Separate compilation for synchronous modules
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Symbolic performance analysis of elastic systems
Proceedings of the International Conference on Computer-Aided Design
Bounded model checking for the existential part of real-time CTL and knowledge
CEE-SET'09 Proceedings of the 4th IFIP TC 2 Central and East European conference on Advances in Software Engineering Techniques
Bounded Model Checking for the Universal Fragment of CTL
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
Conditional Safety Certification of Open Adaptive Systems
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A source-to-source transformation tool for error fixing
CASCON '13 Proceedings of the 2013 Conference of the Center for Advanced Studies on Collaborative Research
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Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDD-based methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graph-based function representations. We focus on several recent advances of particular importance for formal verification and other CAD applications.