ACM Transactions on Programming Languages and Systems (TOPLAS)
Synchronization mechanisms for distributed event-driven computation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
A methodology for HW-SW codesign in ATM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design Automation for Embedded Systems
Verification of electronic systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Rapid Digital System Prototyping: Current Practice, Future Challenges
IEEE Design & Test
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design challenges of high speed ATM communication ASICs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A framework for fast hardware-software co-simulation
Proceedings of the conference on Design, automation and test in Europe
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Common approaches to hardware implementation of networking components start at the VHDL level and are based on the creation of regression test benches to perform simulative validation of functionality. The time needed to develop test benches has proven to be a significant bottleneck with respect to time-to-market requirements. In this paper, we describe the coupling of a telecommunication network simulator with a VHDL simulator and a hardware test board. This co-verification approach enables the designer of hardware for networking components to verify the functional correctness of a device under test against the corresponding algorithmic description and to perform functional chip verification by reusing test benches from a higher level of abstraction.