A system-level co-verification environment for ATM hardware design
Proceedings of the conference on Design, automation and test in Europe
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This presentation will discuss the challenges of the design of the ASICs required by present ATM systems. The problems of such devices are presented based on the experience of Telefonica 1+D. Solutions to some of those problems are also presented, while in other cases the solution is only anticipated and will require new tools and technologies to be provided by the CAE community.