Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A new model for improving symbolic product machine traversal
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A system-level co-verification environment for ATM hardware design
Proceedings of the conference on Design, automation and test in Europe
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Optimizing Symbolic Model Checking for Constraint-Rich Models
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
A constructive approach towards correctness of synthesis-application within retiming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Dependent latch identification in the reachable state space
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a novel verification method for finite state machines (FSMs), which automatically exploits the relation between the state encodings of the FSMs under consideration. It is based on the detection and utilization of functionally dependent state variables. This significantly extends the ability of the verification method to handle FSMs with similar state encodings. The effectiveness of the proposed method is illustrated by experimental results on well-known benchmarks.