Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Least fixpoint approximations for reachability analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Heuristic Algorithms for Early Quantification and Partial
Heuristic Algorithms for Early Quantification and Partial
VERISEC: verifying equivalence of sequential circuits using SAT
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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The large number of latches in current designs increase the complexity of formal verification and logic synthesis, since the growth of latch number leads the state space to explode exponentially. One solution to this problem is to find the functional dependencies among these latches. Then, these latches can be identified as dependent latches or essential latches, where the state space can be constructed using only the essential latches. This paper proposes an approach to find the functional dependencies among latches in a sequential circuit by using SAT solvers with the Craig interpolation theorem. In addition, the proposed approach detects sequential functional dependencies existing in the reachable state space only. Experimental results show that our approach could deal with large sequential circuits with up to 1.5K latches in a reasonable time and simultaneously identify the combinational and sequential dependent latches.