Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Parallel program design: a foundation
Parallel program design: a foundation
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Higher-Level Specification and Verification with BDDs
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Model checking in industrial hardware design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Two forms of dependence in propositional logic: controllability and definability
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A BDD-based satisfiability infrastructure using the unate recursive paradigm
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Optimizing Symbolic Model Checking for Constraint-Rich Models
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Artificial Intelligence
25 Years of Model Checking
Dependent latch identification in the reachable state space
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for memory hierarchies: advanced lectures
Algorithms for memory hierarchies: advanced lectures
Improving static variable orders via invariants
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Journal of Computer and System Sciences
Syntax-driven reachable state space construction of synchronous reactive programs
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
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