Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Trace theory for automatic hierarchical verification of speed-independent circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Verifying a static RAM design by logic simulation
Proceedings of the fifth MIT conference on Advanced research in VLSI
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Validating discrete event simulations using event pattern mappings
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Inductive verification of iterative systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
On computing the transitive closure of a state transition relation
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
A unified approach to language containment and fair CTL model checking
DAC '93 Proceedings of the 30th international Design Automation Conference
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
The complexity of verification
STOC '94 Proceedings of the twenty-sixth annual ACM symposium on Theory of computing
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Calculation of unate cube set algebra using zero-suppressed BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
On the computation of the set of reachable states of hybrid models
DAC '94 Proceedings of the 31st annual Design Automation Conference
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems
EURO-DAC '94 Proceedings of the conference on European design automation
Analysis of switch-level faults by symbolic simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic modeling and evaluation of data paths
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generation of BDDs from hardware algorithm descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Representation and symbolic manipulation of linearly inductive Boolean functions
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Derivation of formal representations from process-based specification and implementation models
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Safe BDD minimization using don't cares
DAC '97 Proceedings of the 34th annual Design Automation Conference
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synthesis of concurrent systems with many similar processes
ACM Transactions on Programming Languages and Systems (TOPLAS)
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
Incremental CTL model checking using BDD subsetting
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
Automatic compositional minimization in CTL model checking
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Verification of systems containing counters
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Symbolic reachability analysis of large finite state machines using don't cares
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Proceedings of the 37th Annual Design Automation Conference
Distance driven finite state machine traversal
Proceedings of the 37th Annual Design Automation Conference
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
Abstraction from counters: an application on real-time systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Efficient verification using generalized partial order analysis
Proceedings of the conference on Design, automation and test in Europe
Application of linearly transformed BDDs in sequential verification
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A 3-step approach for performance-driven whole-chip routing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Parallelizing the Murϕ Verifier
Formal Methods in System Design - Special issue on CAV '97
Quantitative solution of omega-regular games380872
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Ordered binary decision diagrams as knowledge-bases
Artificial Intelligence
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
IEEE Transactions on Computers
Arithmetic Boolean Expression Manipulator Using BDDs
Formal Methods in System Design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
Understanding Integrated Circuits
IEEE Design & Test
A Characterization of Binary Decision Diagrams
IEEE Transactions on Computers
Automated Verification of Behavioral Equivalence for Microprocessors
IEEE Transactions on Computers
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Applying Model Checking in Java Verification
Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Compositional Real-Time Semantics of STATEMATE Designs
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
Stepwise CTL Model Checking of State/Event Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model Checking the World Wide Web
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Handbook of automated reasoning
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
Implicit manipulation of polynomials using zero-suppressed BDDs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Verification and Synthesis of Counters Based on Symbolic Techniques
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Efficient model checking via the equational /spl mu/-calculus
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Timing analysis of industrial real-time systems
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Complexity of many-valued logics
Beyond two
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Irredundant Algorithms for Traversing Directed Graphs: The Nondeterministic Case
Programming and Computing Software
Quantitative solution of omega-regular games
Journal of Computer and System Sciences - STOC 2001
Functional test generation based on word-level SAT
Journal of Systems Architecture: the EUROMICRO Journal
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Toward the formal verification of a unification system
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Toward the formal verification of a unification system
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics - Special issue on cybernetics and cognitive informatics
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verifying statemate statecharts using CSP and FDR
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Model checking dynamic UML consistency
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Combining several paradigms for circuit validation and verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Sigref: a symbolic bisimulation tool box
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Abstract property language for MDG model checking methodology
International Journal of Computer Applications in Technology
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The temporal logic model checking algorithm developed by Clarke, Emerson, and Sistla [9] is modified to represent a state graph using binary decision diagrams (BDD's) [4]. Because this representation captures some of the regularity in the state space of sequential circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 1020 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to handle a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.