Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Lower bounds on the OBDD size of graphs of some popular functions
SOFSEM'05 Proceedings of the 31st international conference on Theory and Practice of Computer Science
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Not long ago, completely automatical formal verification of multipliers was not feasible, even for small input word sizes. However, with Multiplicative Binary Moment Diagrams (*BMD), which is a new data structure for representing arithmetic functions over Boolean variables, methods were proposed by which verification of multipliers with input word sizes of up to 256 Bits is now feasible. Unfortunately, only experimental data has been provided for these verification methods until now.In this paper, we give a formal proof that logic verification with *BMDs is polynomially bounded in both, space and time, when applied to the class of Wallace-tree like multipliers. Using this knowledge online detection of design errors becomes feasible during a verification run.