Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Residue BDD and its application to the verification of arithmetic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Who are the variables in your neighborhood
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A lower bound for integer multiplication with read-once branching programs
STOC '95 Proceedings of the twenty-seventh annual ACM symposium on Theory of computing
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory
Formal Methods in System Design
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Prove that a faulty multiplier is faulty!?
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Non-Abelian Groups in Optimization of Decision Diagrams Representations of Discrete Functions
Formal Methods in System Design
A Unifying Approach to Edge-valued and Arithmetic Transform Decision Diagrams
Automation and Remote Control
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design
A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode
Formal Methods in System Design
Polynomial Formal Verification of Multipliers
Formal Methods in System Design
Model Checking Large Software Specifications
IEEE Transactions on Software Engineering
IEEE Transactions on Software Engineering
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Polynomial Formal Verification of Multipliers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
New methods and coverage metrics for functional verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, here basic building blocks are first shown to implement a word-level specification. The overall circuit functionality is then verified at the word level. Multipliers with word sizes of up to 62 bits have been verified by this technique.