Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Edge-valued binary decision diagrams for multi-level hierarchical verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ACV: an arithmetic circuit verifier
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Dynamic minimization of word-level decision diagrams
Proceedings of the conference on Design, automation and test in Europe
The K*BMD: A Verification Data Structure
IEEE Design & Test
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Implementation of a multiple-domain decision diagram package
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Automatic Datapath Extraction for Efficient Usage of HDD
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits
Verification of Arithmetic Functions with Binary Moment Diagrams
Verification of Arithmetic Functions with Binary Moment Diagrams
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
HDL Constructs in Linear Word-Level Decision Diagram Based Specification
Automation and Remote Control
Representation of Logical Circuits by Linear Decision Diagrams with Extension to Nanostructures
Automation and Remote Control
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
IEEE Transactions on Computers
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Modular datapath optimization and verification based on modular-HED
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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