Microprocessor design verification
Journal of Automated Reasoning
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient validity checking for processor verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Boosting beyond static scheduling in a superscalar processor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Modelling Bit Vectors in HOL: the word library
HUG '93 Proceedings of the 6th International Workshop on Higher Order Logic Theorem Proving and its Applications
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
On Shostak's Decision Procedure for Combinations of Theories
CADE-13 Proceedings of the 13th International Conference on Automated Deduction: Automated Deduction
Formal verification of word-level specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
RTL-Datapath Verification using Integer Linear Programming
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An efficient finite-domain constraint solver for circuits
Proceedings of the 41st annual Design Automation Conference
Using Word-Level Information in Formal Hardware Verification
Automation and Remote Control
Simplify: a theorem prover for program checking
Journal of the ACM (JACM)
Encyclopedia of Computer Science
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Equivalence verification of arithmetic datapaths with multiple word-length operands
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Bit level types for high level reasoning
Proceedings of the 14th ACM SIGSOFT international symposium on Foundations of software engineering
IEEE Transactions on Computers
Fast exact Toffoli network synthesis of reversible logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Verification of arithmetic datapaths using polynomial function models and congruence solving
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable decision procedure for fixed-width bit-vectors
Proceedings of the 2009 International Conference on Computer-Aided Design
Encoding RTL Constructs for MathSAT: a Preliminary Report
Electronic Notes in Theoretical Computer Science (ENTCS)
Deciding bit-vector arithmetic with abstraction
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
A decision procedure for bit-vectors and arrays
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Accurate theorem proving for program verification
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Approximating predicate images for bit-vector logic
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Bounded model checking of software using SMT solvers instead of SAT solvers
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Producing and verifying extremely large propositional refutations
Annals of Mathematics and Artificial Intelligence
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Bit-v ector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended theory which includes arithmetic. Although deciding equality in suc h a theory is NP-hard, our implementation is efficient for many practical examples. We believ e this to be the first such implementation which is efficient, automatic, and complete.