AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
A decision procedure for bit-vector arithmetic
DAC '98 Proceedings of the 35th annual Design Automation Conference
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Equivalence checking of combinational circuits using Boolean expression diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. In this paper we presenta technique generating tests by specifying the don't careinputs in the functional specifications so as to improvetheir coverage of both design errors and manufacturingfaults. The don't cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way require only a fraction of pseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage.