Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Problem-Solving Methods in Artificial Intelligence
Problem-Solving Methods in Artificial Intelligence
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Coarse-Grain Parallelization of Test Vectors Generation on Multiprocessor Systems
IWCC '01 Proceedings of the NATO Advanced Research Workshop on Advanced Environments, Tools, and Applications for Cluster Computing-Revised Papers
A Parallel Transitive Closure Computation Algorithm for VLSI Test Generation
PARA '02 Proceedings of the 6th International Conference on Applied Parallel Computing Advanced Scientific Computing
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
An Approach for Analysing the Propagation of Data Errors in Software
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Process-tolerant test with energy consumption ratio
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
ATS '95 Proceedings of the 4th Asian Test Symposium
A parallel sequential test generation system DESCARTES based on real-valued logic simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
Training diploma students on ATE-related module
ATS '95 Proceedings of the 4th Asian Test Symposium
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Test generation for cyclic combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Test generation for mixed-signal devices using signal flow graphs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High Quality Robust Tests for Path Delay Faults
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ENHANCED DELAY DEFECT COVERAGE WITH PATH-SEGMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
EXPLOITING DON'T CARES TO ENHANCE FUNCTIONAL TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Variation-Tolerant, Power-Safe Pattern Generation
IEEE Design & Test
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel ATPG Method for Capture Power Reduction during Scan Testing
IEICE - Transactions on Information and Systems
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper: Automatic test pattern generation on parallel processors
Parallel Computing
Journal of Electronic Testing: Theory and Applications
Computational complexity in logic testing
INES'10 Proceedings of the 14th international conference on Intelligent engineering systems
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
A test clock reduction method for scan-designed circuits
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Behavioral test generation using mixed integer non-linear programming
ITC'94 Proceedings of the 1994 international conference on Test
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Fault isolation in grey systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Testability features in the TMS370 family of microcomputers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Reconfigurable hardware for Pseudo-exhaustive test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Considering zero-arrival time and block-arrival time in hierarchical functional timing analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Formal Verification and Diagnosis of Combinational Circuit Designs with Propositional Logic
Fundamenta Informaticae
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
GPU-based n-detect transition fault ATPG
Proceedings of the 50th Annual Design Automation Conference
VM image update notification mechanism based on pub/sub paradigm in cloud
Proceedings of the 5th Asia-Pacific Symposium on Internetware
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 14.99 |
The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.