Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
Proceedings of the 37th Annual Design Automation Conference
Symbolic Model Checking
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe
Combining abstraction refinement and SAT-based model checking
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
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Static property checking verifies pre-defined functionaldesign rules such as "bus contention", "racing condition",and "don't-care case". A static property checker typicallyuses formal verification techniques to prove the propertyunder verification. If the property is proven false, a counterexampleis generated for debugging the design. Among thedifferent static property checking approaches, ATPG-basedand BDD-based are the most powerful and successful ones.We implement both approaches with several optimizationtechniques on the same framework to compare their performance.The experimental results on industrial designs showthat these two approaches have different strength and weaknessin proving the static properties. Furthermore, theresults indicate that they often complement each other andtherefore a hybrid approach may result in better performance.We propose a static property checker based on combinedATPG and BDD techniques. The experimental resultsshow that this combined approach can prove all the staticproperties in the testcases while still maintaining comparableperformance.