Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test generation for resistive opens in CMOS
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Debugging Hardware Designs Using a Value-Based Model
Applied Intelligence
Journal of Computer Science and Technology
Using Multiple Models for Debugging VHDL Designs
Proceedings of the 14th International conference on Industrial and engineering applications of artificial intelligence and expert systems: engineering of intelligent systems
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results
Applied Intelligence
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Journal of Computer Science and Technology
| Hi-index | 4.10 |
Test development can be tedious and time-consuming, sometimes stretching over several months for complex designs. In the past two decades, various test development automation tools have attempted to address this problem and reduce the bottleneck in the product's time to market. These tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in this article is on automatic test-pattern- generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology, however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification.