Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
Partial Scan at the Register-Transfer Level
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An ATPG-Based Framework for Verifying Sequential Equivalence
Proceedings of the IEEE International Test Conference on Test and Design Validity
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Testing "untestable" faults in three-state circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Switch-level modeling of transistor-level stuck-at faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
| Hi-index | 0.00 |
Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification.